Precision and attention to detail in digital design
To ensure that a digital design fully meets the required functionality, CTS follows robust specification and documentation processes that enable the creation of efficient, reliable design and test procedures.
Processes, Methodologies and Tools
- Requirements matrix
- Functional verification - Universal Verification Methodology (UVM)
- Constrained-random stimulus and RTL assertions
- Coverage tests
- Design for Testability (DFT)
- Formal equivalence verification
- Automatic Test Pattern Generation (ATPG)
- Tools: ModelSim, Tessent, Questa, Modus, Xcelium, TestMAX, VCS, Vivado, Quartus
- Languages: SystemVerilog, Verilog, VHDL
- Platforms: Synopsys, Cadence, Xilinx, Altera
Application Areas
- Telecommunication protocols
- Computer architectures (including RISC-V)
- Chipset verification platforms
- High-speed buses
- IP cores
